Semiconductor device and its manufacturing method

ABSTRACT

A semiconductor device comprising a wiring suitable for miniaturization and manufacturing method thereof are disclosed. According to one aspect of the present invention, it is provided a semiconductor device comprising an insulator formed above a semiconductor substrate, and a wiring formed in the insulator and having surface roughness capable of suppressing surface scattering of electrons and reduction in electrical conductivity thereof.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a Continuation of U.S. Ser. No. 11/280,812, filedNov. 17, 2005 which is based upon and claims the benefit of priorityfrom prior Japanese Patent Application No. 2005-235318, filed Aug. 15,2005, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device and itsmanufacturing method, and more particularly to a semiconductor devicewhich comprises a wiring suitable for miniaturization, and itsmanufacturing method.

2. Description of the Related Art

With progress of miniaturization of semiconductor devices to achievehigher integration, higher speed operation and higher performancethereof, an increase in wiring resistance owing to miniaturization of awiring is one of the problems.

In a miniaturized semiconductor device, wiring performance is not onlyaffected by properties of a wiring material, feature size, patterningvariation and the like but also dependent on surface roughness of thewiring. To improve wiring performance, technologies of reducing surfaceroughness of a wiring metal or a barrier metal are disclosed, forexample, in U.S. Pat. No. 6,200,894 B1 and U.S. patent application Ser.No. 08/825,216.

U.S. Pat. No. 6,200,894 B1 discloses a technology of improvingelectro-migration resistance in an aluminum wiring and a contact plug.According to this technology, by smoothing an underlying insulator,surface of the aluminum film formed thereon is smoothed, and also a filmstructure, i.e., orientation of crystal grains, is improved, therebyincreasing electro-migration resistance of the aluminum film.

U.S. patent application Ser. No. 08/825,216 discloses a technology offorming a titanium nitride film as a barrier metal with a lowerresistivity and smaller surface roughness by controlling depositionconditions of a titanium nitride film.

In the above technologies, problems caused by a reduced wiring size arenot taken into consideration. J. J. Thomson points out in his theorythat, in a miniaturized semiconductor device, when a wiring width and/ora wiring thickness are close to a mean free path of electrons in thewiring metal, surface roughness of the wiring affects electricalconductivity of the metal wiring (e.g., see pp. 52 to 54 of “PhysicalProperties of Thin Metal Film”, by G. P. Zhigal'skii, B. K. Jones,issued by Taylor & Francis). FIG. 1 shows a relation between a wiringwidth and electrical conductivity of a copper (Cu) wiring calculatedbased on Thomson's theory. In the drawing, a horizontal axis indicates awiring width, and a vertical axis indicates relative electricalconductivity. Here, the relative electrical conductivity (σ_(f)/σ₀) is aratio of electrical conductivity (σ_(f)) in a narrow metal to electricalconductivity (σ0) in a metal having an infinite size (referred to asbulk metal). A mean free path of electrons in Cu at room temperature isknown as about 40 nm. It is shown that when the wiring width becomesnarrower and approaches 40 nm, electrical conductivity reduces rapidly.The reduction in electrical conductivity means an increase inresistance. Such a reduction in electrical conductivity is caused byscattering of electrons due to rough surface of the wiring and reducingin effective mean free path of electrons thereby. By the miniaturizationof the semiconductor device, the wiring width has been approached 40 nmof a mean free path of electrons in Cu.

BRIEF SUMMARY OF THE INVENTION

According to one aspect of the present invention, it is provided asemiconductor device comprising: an insulator formed above asemiconductor substrate; and a wiring formed in the insulator and havingsurface roughness capable of suppressing surface scattering of electronsand reduction in electrical conductivity thereof.

According to another aspect of the present invention, it is provided amethod for manufacturing a semiconductor device, comprising: forming aninsulator above a semiconductor substrate; forming at least one of awiring groove and a contact hole in the insulator; forming a barriermetal in at least one of the wiring groove and the contact hole;smoothing a surface of at least one of the wiring groove, the contacthole and the barrier metal; and forming a copper wiring on the barriermetal.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

FIG. 1 shows a relation between a wiring width and electricalconductivity of a copper wiring calculated based on Thomson's theory;

FIG. 2 is a diagram showing a calculation model based on Thomson'stheory used in an embodiment according to the present invention;

FIG. 3 is a diagram showing a calculation model of a wiring havingsurface roughness according to an embodiment of the present invention;

FIG. 4 is a diagram showing an influence of surface roughness onnormalized electrical conductivity of a Cu wiring calculated accordingto the embodiment of the present invention;

FIG. 5 is a diagram showing an influence of surface roughness onrelative electrical conductivity of the Cu wiring normalized byelectrical conductivity of a thin film Cu wiring having a smooth surfaceand the same thickness calculated according to the embodiment of thepresent invention;

FIG. 6 is a diagram showing an influence of surface roughness on theelectrical conductivity of the Cu wiring having different wiring widthscalculated according to the embodiment of the present invention;

FIG. 7 is a diagram showing a relation between an allowable surfaceroughness and a wiring width of the Cu wiring calculated according tothe embodiment of the present invention;

FIG. 8 is a sectional view of a semiconductor device shown to explain aCu multilevel wiring used in embodiments of the present invention;

FIGS. 9A, 9B are enlarged sectional views of a barrier metal surface toexplain a first embodiment of the present invention;

FIGS. 10A to 10C are sectional views of a wiring structure to explain asecond embodiment of the present invention;

FIG. 11 is a sectional view of an interlevel insulator to explain athird embodiment of the present invention;

FIG. 12A is a plan view of a resist pattern shown to explain a fourthembodiment of the present invention;

FIG. 12B is a sectional view of the resist pattern according to thefourth embodiment;

FIGS. 13A, 13B are plan views of resist patterns shown to explain afifth embodiment of the present invention; and

FIG. 14 is a sectional view of a stacked film for etching shown toexplain a sixth embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The embodiments of the present invention will be described withreference to the accompanying drawings. Throughout the drawings,corresponding portions are denoted by corresponding reference numerals.Each of the following embodiments is illustrated as one example, andtherefore the present invention can be variously modified andimplemented without departing from the spirits of the present invention.

The present invention is directed to a miniaturized semiconductor devicewhich comprises a wiring having predetermined surface roughness.

As miniaturizing the wiring, e.g., a wiring width becomes 100 nm orless, electrons moving in the wiring are scattered by rough surface ofthe wiring to cause a reduction in electrical conductivity, that is, anincrease in wiring resistance. Thus, it is important to control thesurface roughness of the wiring to be small, thereby suppressing theincrease in wiring resistance.

A critical surface roughness of the wiring can be determined byextending Thomson's theory. Thomson's theory argues about effects ofmetal surface roughness on electrical conductivity in a narrow metalwhen a width (or thickness) of the metal is equal to or less than a meanfree path of electrons in the metal. Strictly, Thomson's theory isapplied to a case in which the metal width is equal to or less than themean free path of electrons as described above. However, the theory canbe applied to a metal width of approximately severalfold.

First, based on Thomson's theory, it is calculated that an effectivemean free path l _(eff) of electrons in a thin film wiring smaller inwidth (or thickness) than a mean free path l₀ of electrons in a metal.FIG. 2 shows a calculation model used in one embodiment of the presentinvention, in which an electron at a position z₀ in a wiring with awidth w will be considered. An intersection point between a line drawnfrom the point z₀ in parallel to a z axis and an upper surface of thewiring is set as P₀. A circle whose radius is equal to the mean freepath l₀ of electrons is drawn centered from the point z₀ in a positivedirection of an x axis, and intersection points with the upper and lowersurfaces of the wiring are set as P₁ and P₂, respectively. An angle fromthe point P₀ to the point P₁ intersecting the upper surface (i.e., anangle P₀-z₀-P₁) is set as θ₁, and an angle to the point P₂ intersectingthe lower surface (i.e., an angle P₀-z₀-P₂) is set as θ₀. In this case,if an angle θ from the z axis is smaller than θ₁ or larger than θ₀, theelectron is scattered by the surface of the wiring. Thus, the effectivemean free path l _(eff) of the electron becomes smaller than theoriginal mean free path l₀. According to Thomson's theory, the effectivemean free path l _(eff) of electrons in the thin film metal is given bythe following equation:

$\begin{matrix}{{\overset{\_}{l}}_{eff} = {\frac{1}{w}{\int_{0}^{w}{{z}{\int_{0}^{\pi}{l_{f}\sin \; \theta {\theta}}}}}}} & {{Eq}.\mspace{14mu} (1)}\end{matrix}$

where, l_(f) is a mean free path of electrons in the thin film wiringhaving a smooth surface, which is obtained by the following equation (2)with respect to a size of θ:

$\begin{matrix}{l_{f} = \left\{ \begin{matrix}\frac{w - z_{0}}{\cos \; \theta} & {0 \leq \theta \leq \theta_{l}} \\l_{o} & {\theta_{l} \leq \theta \leq \theta_{0}} \\{- \frac{z_{0}}{\cos \; \theta}} & {\theta_{0} \leq \theta \leq \pi}\end{matrix} \right.} & {{Eq}.\mspace{14mu} (2)}\end{matrix}$

In a thin film metal, a mean free path l _(f) of electrons can berepresented by using an electrical conductivity σ₀ in a bulk metal andelectrical conductivity σ_(f) in the thin film metal. As electricalconductivity σ is proportional to the mean free path l of electrons,their relation is given as follows:

σ_(f)/σ₀ = l _(f) /l ₀   Eq. (3)

The left side of the equation (3) is normalized electrical conductivityσ_(f)/σ₀. Accordingly, by substituting the equation (3) with theequation (1) to calculate, the normalized electrical conductivityσ_(f)/σ₀ is obtained by the following equation:

$\begin{matrix}{\frac{\sigma_{f}}{\sigma_{0}\;} = {\frac{1}{2}{\frac{w}{l_{0}}\left\lbrack {{\ln \left( \frac{l_{0}}{w} \right)} + \frac{3}{2}} \right\rbrack}}} & {{Eq}.\mspace{14mu} (4)}\end{matrix}$

It can be understood from the equation (4) that if the wiring width wbecomes equal to the mean free path l₀ of electrons in the bulk metal,effective electrical conductivity σ_(f) becomes 75% of the electricalconductivity σ₀ of electrons in the bulk metal.

The above discussion is in the case of the wiring with a smooth surface.However, an actual surface of a metal wiring has certain amount ofroughness. Surface roughness of the metal wiring or the like can bemeasured by, e.g., an atomic force microscope (AFM) with an accuracy oforder of 0.1 nm. It is said that actual surface roughness of the metalwiring, e.g., a Cu wiring, is at least about 10 nm. Thus, to consider aninfluence of electron scattering caused by the surface roughness of thewiring, Thomson's theory can be developed as follows.

An actual surface morphology of the metal wiring is not uniform butcomplex shape. To simplify the description, however, the surfacemorphology of the wiring is modeled as shown in FIG. 3. The surface isassumed to be formed into a sine wave shape having amplitude (maximumwidth) of 2 a and a period of s. In this case, front side and backsidesurface shape z₁ and z₂ are given by the following equation:

$\begin{matrix}\left\{ \begin{matrix}{z_{1} = {w + {a\; {\sin \left( \frac{2\pi \; x}{s} \right)}}}} \\{{z_{2} = {a\; {\sin \left( \frac{2\pi \; x}{s} \right)}}}\mspace{45mu}}\end{matrix} \right. & {{Eq}.\mspace{14mu} (5)}\end{matrix}$

An effective mean free path l _(fR) of electrons in the thin film wiringhaving the above surface roughness is obtained by the following equation(6) which is a modification of the equation (1):

$\begin{matrix}{{\overset{\_}{l}}_{fR} = {\frac{1}{w}\; {\int_{0}^{l_{0}}{{x}{\int_{a\; s\; i\; {n{(\frac{2\pi \; x}{s})}}}^{w + {a\; {\sin {(\frac{2\pi \; x}{s})}}}}{{z}{\int_{0}^{\pi}{l_{f}\sin \; \theta {\theta}}}}}}}}} & {{Eq}.\mspace{14mu} (6)}\end{matrix}$

Solving the equation (6), its solution is represented by the followingequation:

$\begin{matrix}{{\overset{\_}{l}}_{fR} = {{\frac{1}{2{wl}_{0}}{\int_{0}^{l_{0}}{\frac{\left( {a\; {\sin \left( \frac{2\pi \; x}{s} \right)}} \right)^{2}}{2}\ln {{a\; \sin \; x}}}}} - {\frac{\left( {w - {a\; {\sin \left( \frac{2\pi \; x}{s} \right)}}} \right)^{2}}{2}\ln {{w - {a\; {\sin \left( \frac{2\pi \; x}{s} \right)}}}}} + {\left( {\frac{1}{2} + {\ln \; l_{0}}} \right)\left\{ {w^{2} - {\frac{1}{2}\left( {{2{aw}\; {\sin \left( \frac{2\pi \; x}{s} \right)}} + w^{2}} \right)}} \right\}} + w^{2} - {\frac{\left( {w + {a\; {\sin \left( \frac{2\pi \; x}{s} \right)}}} \right)^{2}}{2}\ln {{w + {a\; {\sin \left( \frac{2\pi \; x}{s} \right)}}}}} + {\frac{\left( {a\; {\sin \left( \frac{2\pi \; x}{s} \right)}} \right)^{2}}{2\;}\ln {\; {a\; {\sin \left( \frac{2\pi \; x}{s} \right)}}}} + {\left( {\frac{1}{4} + {\frac{1}{2}\ln \; l_{0}}} \right)\left( {{2a\; w\; {\sin \left( \frac{2\pi \; x}{s} \right)}} + w^{2}} \right){x}}}} & {{Eq}.\mspace{14mu} (7)}\end{matrix}$

As in the case of the equation (3), electrical conductivity in the bulkmetal is set as σ₀ and electrical conductivity in the thin film metalhaving roughness is set as σ_(fR). As the electrical conductivity isproportional to the mean free path of electrons, the equation (3) can bemodified to the following equation:

σ_(fR)/σ₀ = l _(fR) /l ₀   Eq. (8)

Accordingly, the electrical conductivity σ_(fR)/σ₀ normalized by usingthe electrical conductivity σ₀ in the bulk metal is represented by thefollowing equation (9) using the equation (7):

$\begin{matrix}{\frac{\sigma_{fR}}{\sigma_{0}\;} = {\frac{{\overset{\_}{l}}_{fR}}{l_{0}} = {{\frac{1}{2w}{\int_{0}^{l_{0}}{\frac{\left( {a\; {\sin \left( \frac{2\pi \; x}{s} \right)}} \right)^{2}}{2}\ln {{a\; \sin \; x}}}}} - {\frac{\left( {w - {a\; {\sin \left( \frac{2\pi \; x}{s} \right)}}} \right)^{2}}{2}\ln {{w - {a\; {\sin \left( \frac{2\pi \; x}{s} \right)}}}}} + {\left( {\frac{1}{2} + {\ln \; l_{0}}} \right)\left\{ {w^{2} - {\frac{1}{2}\left( {{2a\; w\; {\sin \left( \frac{2\pi \; x}{s} \right)}} + w^{2}} \right)}} \right\}} + w^{2} - {\frac{\left( {w + {a\; {\sin \left( \frac{2\pi \; x}{s} \right)}}} \right)^{2}}{2}\ln {{w + {a\; {\sin \left( \frac{2\pi \; x}{s} \right)}}}}} + {\frac{\left( {a\; {\sin \left( \frac{2\pi \; x}{s} \right)}} \right)^{2}}{2}\ln {{a\; {\sin \left( \frac{2\pi \; x}{s} \right)}}}} + {\left( {\frac{1}{4} + {\frac{1}{2}\ln \; l_{0}}} \right)\left( {{2\; {aw}\; {\sin \left( \frac{2\pi \; x}{s} \right)}} + w^{2}} \right){x}}}}} & {{Eq}.\mspace{14mu} (9)}\end{matrix}$

FIG. 4 shows a result of an influence to a normalized electricalconductivity σ_(fR)/σ₀ as a function of the surface roughness byapplying the equation (9) to a Cu wiring with a wiring width w 40 nm. Inthis case, a mean free path of electrons in Cu is set to l₀=40 nm and aperiod of surface roughness is presumed as s=2π (rad). It can beunderstood from FIG. 4 that the electrical conductivity in the thin filmis reduced to 75% of that in the bulk metal even when the surface issmooth. It can be additionally understood that the electricalconductivity is exponentially reduced as the surface roughness becomeslarger. In the case of FIG. 4, the reduction in electrical conductivitybecomes conspicuous when the surface roughness reaches about 10 nm ormore, in other words, when the surface roughness exceeds 25% of the meanfree path of electrons.

As the semiconductor device is miniaturized further, it is required tosuppress an increase in resistance of a multilevel wiring. It is knownthat a resistance value of the wiring of the semiconductor device variesdue to various factors. For example, the factors include a variation inpatterning size of the wiring, a variation in film thickness of thewiring, a variation in resistivity of the wiring material itself, andthe like. Smaller variations are preferable. To suppress a resistancevariation of the overall semiconductor device to 10% or less, anincrease in resistivity of the wiring metal itself, i.e., a reduction inelectrical conductivity, must be controlled to, e.g., 2%, or less fromthe standpoint of designing the semiconductor device.

As means therefor, the surface of the wiring may be smoothed to reducesurface roughness which causes a reduction in electrical conductivity.Thus, when the equation (9) is modified and normalized by usingelectrical conductivity σ_(f) of a wiring with the same wiring width whaving a smooth surface in place of the electrical conductivity of thebulk metal σ₀, it is represented by the following equation:

$\begin{matrix}{\frac{\sigma_{fR}}{\sigma_{f}} = {\frac{{\overset{\_}{l}}_{fR}}{{\overset{\_}{l}}_{f}} = {{\frac{l_{0}}{2w{\overset{\_}{l}}_{f}}{\int_{0}^{l_{0}}{\frac{\left( {a\; {\sin \left( \frac{2\pi \; x}{s} \right)}} \right)^{2}}{2}\ln {{a\; \sin \; x}}}}} - {\frac{\left( {w - {a\; {\sin \left( \frac{2\pi \; x}{s} \right)}}} \right)^{2}}{2\;}\ln {{w - {a\; {\sin \left( \frac{2\pi \; x}{s} \right)}}}}} + {\left( {\frac{1}{2} + {\ln \; l_{0}}} \right)\left\{ {w^{2} - {\frac{1}{2}\left( {{2\; {aw}\; {\sin \left( \frac{2\pi \; x}{s} \right)}} + w^{2}} \right)}} \right\}} + w^{2} - {\frac{\left( {w + {a\; {\sin \left( \frac{2\pi \; x}{s} \right)}}} \right)^{2}}{2}\ln {{w + {a\; {\sin \left( \frac{2\pi \; x}{s} \right)}}}}} + {\frac{\left( {a\; {\sin \left( \frac{2\pi \; x}{s} \right)}} \right)^{2}}{2}\ln {\; {a\; {\sin \left( \frac{2\pi \; x}{s} \right)}}}} + {\left( {\frac{1}{4} + {\frac{1}{2}\ln \; l_{0}}}\; \right)\left( {{2\; {aw}\; {\sin \left( \frac{2\pi \; x}{s} \right)}} + w^{2}} \right){x}}}}} & {{Eq}.\mspace{14mu} (10)}\end{matrix}$

FIG. 5 shows a result of a calculation on an influence of surfaceroughness on relative electrical conductivity σ_(fR)/σ_(f) normalized byelectrical conductivity σ_(f) of a thin film metal with a smooth surfaceand the same thickness by applying the equation (10) to a Cu wiring witha wiring width 40 nm, as in the case of FIG. 4. To suppress an increasein resistivity of the wiring, i.e., a reduction in electricalconductivity, to 2% or less in the miniaturized Cu wiring, it can beunderstood from FIG. 5 that surface roughness must be controlled to 10nm or less in the case of the wiring with 40 nm wide.

FIG. 6 similarly shows a result of calculating an influence of surfaceroughness on relative electrical conductivity σ_(fR)/σ_(f) of a wiringin the case of a Cu wiring with a wiring width of 10 nm to 40 nm. It canbe understood from FIG. 6 that to suppress a reduction in relativeelectrical conductivity to 2% or less, for example, allowable surfaceroughness Ra is about 3.6 nm or less in the Cu wiring with 10 nm wide.Similarly, allowable surface roughness Ra is 5.9 nm or less in a wiringwidth of 20 nm, and 8.3 nm or less in a wiring width of 30 nm.

FIG. 7 shows a relation between allowable surface roughness Ra and awiring width w calculated to each of Cu wirings with wiring width of 10nm to 100 nm, as described above. A line interconnecting points in FIG.7 is calculated by a least square method, for the Cu wiring with awiring width of 100 nm or less, the allowable surface roughness isobtained as a function of the wiring width w by the following equation:

Ra≦1.06+0.26 w−0.97×10⁻⁴ w²   Eq. (11).

For simplicity, the above calculation has been described by consideringthe surface having fixed roughness repeatedly. In the actual wiring,however, the surface is constituted of a complex roughness, in whichroughness with various amplitude and periods are mixed, and theroughness in which amplitude and periods thereof are larger and/orsmaller than that of the model is arranged at random. Thus, the surfaceroughness calculated above can be rephrased to correspond to meansurface roughness Ra in the actual wiring.

As apparent from the aforementioned discussion, even when the patterningsize of the wiring changes, by controlling the mean surface roughness Raof the Cu wiring to be within a range satisfying the equation (11) withrespect to the wiring width w, it can be suppressed a reduction inelectrical conductivity of the Cu wiring to 2% or less.

Thus, in the miniaturized semiconductor device, the surface roughness Raof the wiring can be quantitatively determined with respect to thedesigned wiring width w, thereby a wiring having surface roughness basedon a result thereof can be designed and manufactured.

Next, a semiconductor device in which surface roughness of a wiring iscontrolled, i.e., smoothed, to meet the equation (11) and itsmanufacturing method will be described by way of some embodiments.However, the semiconductor device and its manufacturing method are notlimited to the embodiments.

To make a surface of the wiring, especially Cu wiring, smooth, variousmethods are available, e.g., a method of smoothing a surface of anunderlying layer, such as an interlevel insulator or a barrier metal,formed the wiring thereon, smoothing a resist for patterning or anetching mask, and the like. The embodiments of smoothing the wiringsurface will be described below by taking Cu wiring as an example.

First Embodiment

A first embodiment of the present invention is directed to asemiconductor device which comprises a wiring with small surfaceroughness formed on a smoothed barrier metal as an underlying layer fora Cu wiring, and its manufacturing method.

FIG. 8 is a sectional view of the semiconductor device to explain a Cumultilevel wiring. To simplify the description, Cu wirings 18, 28 of twolayers are shown. According to the embodiment, a first interlevelinsulator 12 is formed over an active element (not shown) such as ametal oxide semiconductor field effect transistor (MOSFET) formed on asemiconductor substrate 10, e.g., a silicon substrate, and planarizedits surface by, e.g., chemical mechanical polishing (CMP). A firstwiring groove 18 t is formed in the first interlevel insulator 12, andthe first wiring 18 is formed therein via a first barrier metal 14. Afirst diffusion preventive film 20 is formed on an entire surface of thefirst wiring 18 and the first interlevel insulator 12. A secondinterlevel insulator 22 is formed on the first diffusion preventive film20. In the second interlevel insulator 22, a contact hole 26 h to beconnected a second wiring 28 to the first wiring 18 and a second wiringgroove 28 t are formed. In the contact hole 26 h and the second wiringgroove 28 t, a contact plug 26 and the second wiring 28 are formed via asecond barrier metal 24. A second diffusion preventive film 30 is formedon an entire surface of the second wiring 28 and the second interlevelinsulator 24 to complete a structure shown in FIG. 8.

The interlevel insulators 12, 22 are preferably low dielectric constantinsulators. For example, an organic silicon film such as a methylsiloxane film containing siloxane such as SiOC or SiOCH, an organic filmsuch as polyallylene ether, or a porous film thereof can be used. Thebarrier metals 14, 24 are conductive films to prevent wiring materialfrom diffusing out. For example, tantalum (Ta), tantalum nitride (TaN),or titanium nitride (TiN) can be used. For the diffusion preventivefilms 20, 30, an insulator capable of preventing Cu diffusion, e.g., asilicon nitride film (SiN film), can be used.

The Cu wiring 28 can be formed by a so-called single or dual damasceneto deposit Cu 28 m in the wiring groove 28 t and/or the contact hole 26h formed in the interlevel insulator 22 by, e.g., electro-plating. Whenthe Cu 28 m is deposited by the electro-plating, the Cu 28 m isdeposited not only in the wiring groove 28 t and the contact hole 26 hbut also on the surface of the interlevel insulator 22. Therfore, afterthe deposition of the Cu 28 m, the Cu 28 m deposited other than in thewiring groove 28 t is removed by, e.g., CMP. For example, this CMP isexecuted in two steps. At the first step, the thickly deposited Cu 28 mis removed by using the barrier metal 24 deposited on the surface of theinterlevel insulator 22 as a stopper. Subsequently, the barrier metal 24and the Cu 28 m on the interlevel insulator 22 are removed by a methodcalled barrier CMP to complete the wiring 28.

FIGS. 9A and 9B are enlarged sectional views of the surface of thecontact hole 26 h and/or the wiring groove 28 t to explain theembodiment. Referring to FIG. 9A, a surface of the barrier metal 24formed on a surface of the contact hole 26 h or the wiring groove 28 tis not always smooth. Surface roughness of each of the Cu wiring 28 andthe contact plug 26 deposited on the surface of the underlying barriermetal 24 having such large surface roughness inevitably becomes large.

Thus, as shown in FIG. 9B, before Cu is deposited, a liquid capable ofpolishing, e.g., CMP slurry 40, is supplied and circulated in the wiringgroove 28 t and the contact hole 26 h to smooth the surface of thebarrier metal 24. As the CMP slurry 40 contains polishing abrasives 40 aand an etchant, convex parts constituting the roughness of theunderlying layer can be selectively polished and removed. For thesmoothing of the barrier metal 24, a slurry having high polishingefficiency to the barrier metal, e.g., the slurry for the barrier CMPdescribed above, is preferable. By depositing Cu on a smoothed surfaceof the barrier metal 24, it can be formed a Cu wiring 28 whose meansurface roughness is controlled to be small.

Thus, in the wiring with a wiring width of 100 nm or less, the meansurface roughness of the wiring can be controlled within a range definedby the equation (11) with respect to the wiring width. Thus, it isprovided a semiconductor device capable of suppressing a reduction inelectrical conductivity caused by surface roughness of a wiring to 2% orless, and its manufacturing method.

Accordingly, in the miniaturized semiconductor device, it is provided asemiconductor device, which can be determined surface roughness of awiring quantitatively and comprises a wiring having surface roughnessdesigned based on a result thereof, and its manufacturing method.

Second Embodiment

A second embodiment of the present invention is directed to asemiconductor device which comprises a wiring with small surfaceroughness formed on a smoothed surface of a low dielectric constantinsulator used as an interlevel insulator, and its manufacturing method.

When a feature size of a semiconductor device is reduced to, forexample, 100 nm or less, a low dielectric constant insulator with aspecific dielectric constant of 3.0 or less, or more preferably 2.5 orless, is desired as an interlevel insulator to reduce parasiticcapacitance of a wiring. FIGS. 10A to 10C are sectional views of awiring structure to explain the embodiment. As shown in FIG. 10A, such alow dielectric constant insulator 22 is generally a porous organicsilicon film or organic film. When a wiring groove 28 t or a contacthole 26 h is patterned in the porous low dielectric constant insulator22 by, e.g., anisotropic etching, in the vicinity of the patternedsurface of the low dielectric constant insulator 22, for example, carbonis released from the insulator to form processing damage or a processdamaged layer 22D. As the process damaged layer 22D is low in mechanicalstrength, surface roughness may be enlarged by the processing damage,like a portion surrounded by a circle A in FIG. 10A, or a part of abarrier metal is oxidized by moisture or the like released from theprocess damaged layer 22D to increase surface roughness.

Therefore, as shown in FIG. 10B, before a barrier metal 24 is formed,damage repair agent 42 is supplied to the damaged layer in, e.g., liquidor gas phase, and then heated to cause reaction to supply carbon to theprocess damaged layer 22D in the near surface of the low dielectricconstant insulator. Specifically, the etched surface is heated in anatmosphere containing the damage repair agent 42, e.g.,hexamethyl-di-silazane (HMDS), at a temperature of 150° C. to 350° C.Accordingly, a carbon concentration and/or a film density in the surfaceof the process damaged layer 22D is recovered equal to or more thanthose in the bulk, thereby a recovered layer 22R can be formed.

As shown in FIG. 10C, Cu is deposited via the barrier metal 24 on therecovered layer 22R of the low dielectric constant insulator (interlevelinsulator) 22 in which damage is recovered and the surface is smoothed.Accordingly, it can be formed a contact plug 26 and a Cu wiring 28 whosemean surface roughness is controlled to be small.

Thus, in the wiring with a wiring width of 100 nm or less, the meansurface roughness of the wiring can be controlled within a range definedby the equation (11) with respect to the wiring width, as in the case ofthe first embodiment. Accordingly, it is provided a semiconductor devicecapable of suppressing a reduction in electrical conductivity caused bysurface roughness of the wiring to 2% or less, and its manufacturingmethod.

Third Embodiment

A third embodiment of the present invention is directed to asemiconductor device which comprises a Cu wiring with small surfaceroughness formed on a smoothed surface by sealing pores 23 on surfacesof a wiring groove 28 t and a contact hole 26 h formed in a porous lowdielectric constant insulator as an interlevel insulator 22, and itsmanufacturing method.

FIG. 11 is a sectional view of an interlevel insulator to explain theembodiment. The pore 23 in a patterned surface of the porous interlevelinsulator 22 can be sealed by using a coating film 44 of, e.g., SiC,SiOC, SiCN or the like. When a barrier metal 24 is deposited on thesurface of the porous interlevel insulator 22, the barrier metal 24 maynot be deposited well on the pore 23 portions. However, when a film suchas the coating film 44 is deposited on the surface of the interlevelinsulator 22 by, e.g., chemical vapor deposition (CVD), plasma-enhancedCVD (PECVD), or atomic layer deposition (ALD), the pore 23 on thesurface can be sealed. By depositing the barrier metal 24 on such asmoothed surface by sealing the pore 23 in the etched surface of theinterlevel insulator 22 as described above, the barrier metal 24 can beuniformly deposited, and its surface can be smoothed, as shown in FIG.11B.

By depositing Cu on the smoothed surface of the barrier metal 24, it canbe formed a Cu wiring (not shown) having small mean surface roughness.

Thus, in a wiring with a wiring width of 100 nm or less, the meansurface roughness of the wiring can be controlled within a range definedby the equation (11) with respect to the wiring width. Accordingly, itcan be provided a semiconductor device capable of suppressing areduction in electrical conductivity caused by surface roughness of awiring to 2% or less, and its manufacturing method.

Fourth Embodiment

A fourth embodiment of the present invention is directed to asemiconductor device which comprises a Cu wiring with a small surfaceroughness formed in a smoothed wiring groove and contact hole in aninterlevel insulator 22 patterned by using a resist pattern havingsmoothed surface as a mask, and its manufacturing method.

A pattern of a resist 46 patterned by lithography may comprise a roughedge surface, for example, as shown in FIG. 12A. If the interlevelinsulator 22 is etched by using such a resist 46 with rough edge as amask to form a wiring groove and/or a contact hole, roughness of theresist 46 is transferred to a patterned surface of the interlevelinsulator 22 to form a wiring groove and/or a contact hole having arough surface.

Therefore, as shown in a sectional view of FIG. 12B, after forming apattern of a wiring groove in the resist 46, for example, a smoothingfilm 48 such as a water-soluble organic film or a water-soluble polymerfilm is formed on the resist pattern by, e.g., a coating method. Thissmoothing film 48 is formed only on the resist 46. The rough patternedge surface of the resist 46 is covered with the smoothing film 48 andthus smoothed. For the smoothing film 48, for example, a water-solubleorganic film or a water-soluble polymer film used in a process ofresolution enhancement lithography assisted by chemical shrink (RELACS)can be used.

The interlevel insulator 22 is etched by using the resist 46 with thesmoothed pattern as a mask, whereby a wiring groove and a contact holehaving smoothed surfaces can be formed. By depositing a barrier metaland Cu in the wiring groove and the contact hole having smoothedsurface, it can be formed a Cu wiring with small mean surface roughness.

Thus, in the wiring with a wiring width of 100 nm or less, the meansurface roughness of the wiring can be controlled within a range definedby the equation (11) with respect to the wiring width. Accordingly, itcan be provided a semiconductor device capable of suppressing areduction in electrical conductivity caused by surface roughness of awiring to 2% or less, and its manufacturing method.

Fifth Embodiment

A fifth embodiment of the present invention is directed to asemiconductor device which comprises a Cu wiring with small surfaceroughness formed in a wiring groove 28 t and a contact hole 26 h havingsmooth surfaces formed in an interlevel insulator 22 by smoothing anedge of a resist pattern by multiple exposures, and its manufacturingmethod.

When the resist pattern is formed by only one exposure, roughness mayoccur in an edge surface of a resist 46, for example, as shown in theplane view of FIG. 12A. Therefore, exposure to the resist is repeated bya plurality of times. Although current exposure device is controlled bya computer to exhibit good reproducibility, even when multiple exposuresare carried out at the same position, for each exposure, an exposureposition may slightly be change in nm order and an amount of defocusingmay also slightly be varied. Thus, as shown in a plane view of FIG. 13A,exposure is repeated to average exposing amounts at the pattern edge,whereby a pattern 46 a of a resist having a smoothed edge surface can beformed as shown in FIG. 13B.

According to the embodiment, as in the case of the fourth embodiment, bysmoothing the resist pattern, it can be formed a smooth wiring grove andcontact hole, thereby forming a Cu wiring having small mean surfaceroughness therein.

Thus, in the wiring with a wiring width of 100 nm or less, the meansurface roughness of the wiring can be controlled within a range definedby the equation (11) with respect to the wiring width. Accordingly, itcan be provided a semiconductor device capable of suppressing areduction in electrical conductivity caused by surface roughness of awiring to 2% or less, and its manufacturing method.

Sixth Embodiment

A sixth embodiment of the present invention is directed to asemiconductor device which comprises a Cu wiring with small surfaceroughness formed in a wiring groove and a contact hole having smoothedsurface formed in an interlevel insulator 22 patterned by using asmoothed hard mask pattern for etching the interlevel insulator 22, andits manufacturing method.

According to the embodiment, as shown in a sectional view of FIG. 14, onthe interlevel insulator 22 to be formed the wiring groove and thecontact hole therein, an etching stacked film 50 that comprises two ormore films having different etching characteristics, e.g., an insulator50 a and an organic film 50 b, is formed. For example, a coating typeSiO₂ film such as polysiloxane can be used for the insulator 50 a, and acoating type organic film such as a carbon film can be used for theorganic film 50 b. A resist pattern is formed on the etching stackedfilm 50.

When the etching stacked films 50 a and 50 b formed as above havingdifferent etching characteristics are sequentially etched while anetching gas is changed by layer, roughness of a patterned edge surfaceis smoothed as etching progresses layer by layer. That is, after etchingthe etching stacked film 50 of two layers shown in FIG. 14, an edgesurface of the organic film 50 b is smoother than that of a resistpattern 46, and an edge surface of the insulator 50 a in the lower layeris much smoother than that of the organic film 50 b. The example of theetching stacked film 50 of the two layers has been described. Effect ofthe smoothing is greater as the number of stacked layers is more and asa film thickness of each layer is thicker. Thus, a pattern of theinsulator 50 a formed just above the interlevel insulator 22 can be madesmoother than that of the resist pattern 46. The interlevel insulator 22is etched by using the smoothed insulator 50 a as a hard mask, a wiringgroove and a contact hole having smooth surfaces can be formed therein.

Accordingly, by smoothing the surfaces of the wiring groove and thecontact hole, it can be formed a Cu wiring having small mean surfaceroughness.

Thus, in the wiring with a wiring width of 100 nm or less, the meansurface roughness of the wiring can be controlled within a range definedby the equation (11). Accordingly, it can be provided a semiconductordevice capable of suppressing a reduction in electrical conductivitycaused by surface roughness of a wiring to 2% or less, and itsmanufacturing method.

As described above, according to the present invention, it can bequantitatively determined a surface roughness Ra of a wiringcorresponding to a wiring width w in a miniaturized semiconductor deviceand provided a semiconductor device which comprises a wiring havingsurface roughness Ra designed based on a result thereof and suitable forminiaturization.

Additional advantages and modifications will readily occur to thoseskilled in the art. Therefore, the invention in its broader aspects isnot limited to the specific details and representative embodiments shownand described herein. Accordingly, various modifications may be madewithout departing from the spirit or scope of the general inventiveconcept as defined by the appended claims and their equivalents.

1. (canceled)
 2. A semiconductor device comprising: an insulator formedabove a semiconductor substrate; a barrier metal formed in theinsulator, the barrier metal having a surface contacting with theinsulator, and the surface having a surface roughness capable ofsuppressing surface scattering of electrons and reduction in electricalconductivity thereof; and a wiring formed on the barrier metal, whereinthe surface roughness Ra is represented by a following equation:Ra≦1.06+0.26 w−0.97×10⁻⁴ w² where w is a width of the wiring, whereinthe width of the wiring is 100 nm or less.
 3. The semiconductor deviceaccording to claim 2, wherein the wiring is formed directly on thebarrier metal.
 4. The semiconductor device according to claim 2, whereinthe wiring is formed in at least one of a wiring groove or a contacthole in the insulator.
 5. The semiconductor device according to claim 2,wherein the wiring is a copper wiring.
 6. The semiconductor deviceaccording to claim 2, wherein the wiring is formed directly on anunderlying layer having a smoothed surface.
 7. The semiconductor deviceaccording to claim 6, wherein the underlying layer is a coatingcomprising at least one of SiC, SiOC, or SiCN.
 8. The semiconductordevice according to claim 2, wherein the wiring has a width equal to orless than a mean free path of electrons in a wiring material.
 9. Thesemiconductor device according to claim 2, wherein the insulator is aporous organic silicon film or an organic film.
 10. The semiconductordevice according to claim 2, wherein the insulator has a dielectricconstant of 2.5 or less.
 11. A method for manufacturing a semiconductordevice, comprising: forming an insulator above a semiconductorsubstrate; forming at least one of a wiring groove or a contact hole inthe insulator; smoothing a surface of at least one of the wiring grooveor the contact hole to form a smoothed surface; forming a barrier metalon the smoothed surface in at least one of the wiring groove or thecontact hole, a barrier metal surface of the barrier metal contactingthe smoothed surface; and forming a copper wiring on the barrier metal,wherein the surface roughness Ra of the barrier metal surface isrepresented by a following equation: Ra≦1.06+0.26 w−0.97×10⁻⁴ w² where wis a width of the wiring, wherein the width of the wiring is 100 nm orless.
 12. The method according to claim 11, wherein the smoothing thesurface comprises: forming a mask pattern comprising a smooth edgesurface, and forming at least one of the wiring grove or the contacthole in the insulator by using the mask pattern.
 13. The methodaccording to claim 12, wherein the forming the mask pattern comprises:forming a resist pattern above the insulator; and forming a smoothingfilm on the resist pattern.
 14. The method according to claim 11,wherein the smoothing the surface comprises: exposing the surface of theat least one of the wiring groove or the contact hole to a damage repairagent; and heating the damage repair agent to cause a reaction with thesurface of the at least one of the wiring groove or the contact hole.15. The method according to claim 14, wherein the damage repair agentcomprises hexamethyl-disilazane (HMDS).
 16. The method according toclaim 11, wherein the insulator is a porous organic silicon film or anorganic film and the forming the at least one of the wiring groove orthe contact hole comprises anisotropically etching the insulator. 17.The method according to claim 11, wherein the wiring has a width equalto or less than a mean free path of electrons in a wiring material. 18.The method according to claim 11, wherein the wiring is formed directlyon the barrier metal.
 19. The method according to claim 11, wherein thewiring is formed directly on an underlying layer having a smoothedsurface.
 20. The method according to claim 19, wherein the underlyinglayer is a coating comprising at least one of SiC, SiOC, or SiCN. 21.The method according to claim 11, wherein the insulator has a dielectricconstant of 2.5 or less.